ulysses 寫:janusng 寫:x86 ISA 是不是 CISC?
P4 是不是 x86 ISA?
A = B , B = C
=> A = C
以子之矛攻子之盾:
janusng 會不會說英文?
美國人會不會說英文?
A=B, B=C => A=C
所以可得出結論:janusng 是美國人。
這種邏輯正確嗎?
只有美國人能說英文嗎?
只有 CISC 能執行 X86 ISA 嗎?
Keyword 是在一個「是」(is /is an element of)上!
「說」(speak)字的比較,在邏輯上/數學運算中,是不存在的。
美國人的定義,和所說的語言無關。
但 CISC/RISC 的定義上,只在 ISA 上。
Superscalar、Pipelining 只是 RISC 的 commonly found features,不是 RISC 的定義。
這和大多美國人說英語一樣,「說英語」,不是美國人的定義!
第一代 ARM 也無 Superscalar、無 Pipeline、無 emulation,但也是 RISC!
wikipedia 的項目,第一行便開宗明議說明了,CISC / RISC 是定義在「microprocessor instruction set architecture」上。
RISC 只 favor 「smaller and simpler set of instructions that all take about the same amount of time to execute」
而 CISC 就 「each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction」
x86 的 ISA 擁有不能叫作「smaller and simpler set of instructions that all take about the same amount of time to execute」的 instructions。
雖然再有人以 load/ store instructions 存在與否作分類,但這個也是 common features / characteristics,和定義無關!
能夠執行 x86 ISA 的 CPU 自然不是 RISC。同樣地,能夠執行 68k ISA 的,也不是 RISC。
在 processor 分類上,所有非 RISC MPU,也就是 CISC,並沒有第三類或不能分類的 MPU!
閣下不會,不代表不存在。RISC 一字,來自 UC Berkerly 的 computer architecture researcher and professor,David Patterson。
強烈建議 ulysses 細讀 Real World Tech, Paul DeMone 寫的
RISC vs. CISC Still Matter
The primary commandment of the RISC design philosophy is no instruction or addressing mode whose function can be implemented by a sequence of other instructions should be included in the ISA unless its inclusion can be quantitatively shown to improve performance by a non-trivial amount, even after accounting for the new instruction's negative impact on likely hardware implementations in terms of increased data path and control complexity, reduction in clock rate, and conflict with efficient implementation of existing instructions. A secondary axiom was that a RISC processor shouldn't have to do anything at run time in hardware that could instead be done at compile time in software. This often included opening up aspects of instruction scheduling and pipeline interlocking to the compilers code generator that were previously hidden from software by complex and costly control logic.
說到 RISC 精神,從來都無提及過 Emulator 與 Pipeline。別硬塞一堆別人沒有說的字眼入 David Patterson 口中!