【事求人】美國一公司徵求半導體專才

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景氣似乎開始回升，收到這樣的求才廣告，貼在這裡看有沒有人有興趣。如有不妥，請版主刪去。謝謝。

If you or your friends are interested in the job positions described below, please contact Dr. Chen at
nchen@hpl.com
Thanks.

------------------------------------ Job Descriptions -----------------------------
1)Job Title: Sr. Member Technical Staff

Job Location: Austin or Dallas, TX

Job Description: YIELD ENHANCEMENT ENGINEER

This challenging position will provide leadership opportunities in defining emerging technical requirements for advanced yield optimization software solutions. This position offers a close working relationship with IP developers defining design solutions for yield and manufacturability. Successful candidates will provide direct technical guidance and definition of best practice yield analysis approaches for future optimization and differentiation of HPL’s yield analysis software solutions.

Engineers will gain responsibility rapidly with experience and will enjoy participation in a fast growing entrepreneurial venture. Our mission is to assist our customers to accelerate the time required to perform technology development and production yield ramp by 50%.

Job Requirements: PhD, MS or BS EE
Must have >5 years experience in yield enhancement capacities with particular knowledge of sub-0.18 um process integration with Cu/low-K metallization schemes, parametric data analysis, and memory and bitmap analysis. Experience with commercial yield optimization software packages is desired with background in pilot-line and large-volume manufacturing environments. Successful candidates will demonstrate strong leadership, management, and interpersonal skills.


2)Job Title: Sr. Member Technical Staff

Job Location: Austin, TX or Dallas, TX

Job Description: MEMORY PRODUCT DEVELOPMENT ENGINEER

This challenging position will provide hands-on experience developing memory and array architectures for purposes of technology development and yield enhancement. Duties of the product development engineer include development of novel array-based designs, with particular focus on Design for Test (DFT) and self-testable architectures, for yield learning applications. Additional responsibilities would include circuit electrical de-bug, and memory test data analysis. Finally, this position would include project leadership of a small, highly technical design implementation team, and appropriate training/mentoring of the same. This exciting position offers a close working relationship with our SRAM and arrays design team, as well as direct involvement with customer engineering and engineering management teams.

Engineers will gain responsibility rapidly with experience and will enjoy participation in a fast growing entrepreneurial venture. Our mission is to assist our customers to accelerate the time required to perform technology development and production yield ramp by 50%.

Job Requirements: MSEE or BSEE.

Must have >5 years experience in SRAM or flash memory product design. Experience should include proven proficiency in memory design with particular knowledge in DFT and self-testable architectures. Additional experience in redundancy design approaches, electrical test and design characterization, and formal EDA verification routines is preferred. Strong leadership and interpersonal skills are required.


Company Profile:
HPL Technologies, Inc. is a leading provider of yield optimization software solutions, enabling semiconductor and flat panel industries to enhance their overall yield. HPL Technologies offers the most complete proven yield optimization software in the market place scaling from a few users to entire global enterprise. That's why it's the choice of the top 25 semiconductor and flat panel manufacturers in the world. HPL's solution empowers companies to accelerate the process of identify, measure, and correct sources of failure in the production process.